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AD1845 15 COMPRESSED INPUT DATA

MSB

15 EXPANSION

3/2

MSB

The AD1845 operates from a +5 V power supply. Independent analog and digital supplies are recommended for optimal performance though excellent results can be obtained in single-supply systems. A voltage reference is included on the codec and its 2.25 V buffered output is available on an external pin (VREF). The reference output can be used for biasing op amps used in dc coupling. The internal reference is externally bypassed to analog ground at the VREF_F pin.

0

2/1

LSB

15 DAC INPUT

Power Supplies and Voltage Reference

0

8 7 LSB

0

3/2

2/1

LSB

MSB

000/00

Figure 2. µ -Law or A-Law Expansion

Clocks and Sample Rates

When 8-bit companding is specified, the ADCs’ linear output is compressed to the format specified. 0

15 ADC OUTPUT

MSB

LSB

15 TRUNCATION

15 COMPRESSION

3/2

MSB

MSB

2/1

0

LSB

0

8 7 LSB

00000000

Figure 3. µ -Law or A-Law Compression

Note that all format conversions take place at input or output. Internally, the AD1845 always uses 16-bit linear PCM representations to maintain maximum precision. Timer Registers

The timer registers are provided for system level synchronization, and for periodic interrupt generation. The 16-bit timer time base is determined by the frequency of the connected input clock source. The timer is enabled by setting the Timer Enable bit, TE, in the Alternate Feature Enable register. To set the timer, load the Upper and Lower Timer Bits Registers. The timer value will then be loaded into an internal count register with a value of approximately 10 µs (the exact timer value is listed in the register descriptions). The internal count register will decrement until it reaches zero, then the Timer Interrupt bit, TI, is set and an interrupt will be sent to the host. The next timer clock will load the internal count register with the value of the Timer Register, and the timer will be reinitialized. To clear the interrupt, write to the Status Register or write a “0” to TI.

The AD1845 operates from a single external crystal or clock source. From a single input, a wide range of sample rates can be generated. The AD1845 default frequency source is a 24.576 MHz input. The AD1845 can also be driven from a 14.31818 MHz (OSC), 24 MHz, 25 MHz or 33 MHz input frequency source. In MODE1, the input drives the internal variable sample frequency generator to derive the following AD1848 compatible sample rates: 5.5125, 6.615, 8, 9.6, 11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1, 48 kHz. In MODE2, the AD1845 can be programmed to generate any sample frequency between 4 kHz and 50 kHz with 1 Hz resolution. Note that it is no longer required to enter Mode Change Enable (MCE) to change the sample rate. This feature allows the user to change the AD1845’s sample rate “on the fly.” CONTROL REGISTERS Control Register Architecture

The AD1845 SoundPort Stereo Codec accepts both data and control information through its byte-wide parallel port. Indirect addressing minimizes the number of external pins required to access all 37 of its byte-wide internal registers. Only two external address pins, ADR1:0, are required to accomplish all data and control transfers. These pins select one of five direct registers. (ADR1:0 = 3 addresses two registers, depending on whether the transfer is for a playback or capture.)

Interrupts

The INT bit, located in the Status Register, is set when the AD1845 cannot respond to parallel bus cycle. The INT sticky bit indicates the status of the AD1845’s internal interrupt logic. This bit is cleared by any host write of any value to the Status Register. The IEN bit of the Pin Control Register determines whether the interrupt pin responds to an interrupt condition and reflects the interrupt state on INT. The AD1845 supports interrupt conditions generated by DMA playback count expiration, DMA capture count expiration, or timer expiration. The INT bit will remain set, HI, until a write has been completed to the Status Register or by clearing the TI, CI, or PI bit (depending on the existing condition) in the Capture Playback Timer Register.

REV. B

–11–

ADR1:0

Register Name

0 1 2 3

Index Address Register Indexed Data Register Status Register PIO Data Register Figure 4. Direct Register Map


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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