Файл:AD1845.pdf

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AD1845 Status Register (ADR1:0 = 2) ADR1:0

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

2

INT

Data 7 CU/L

CL/R

CRDY

SOUR

PU/L

PL/R

PRDY

INT

Interrupt Status. This sticky bit (the only one) indicates the status of the interrupt logic of the AD1845. This bit is cleared by any host write of any value to this register. The IEN bit of the Pin Control Register determines whether the state of this bit is reflected on the INT pin of the AD1845. The only interrupt conditions supported by the AD1845 are generated by the underflow of the DMA Current Count Register or the Timer Registers. 0 1

PRDY

Playback Data Register Ready. The PIO Playback Data Register is ready for more data. This bit should only be used when direct programmed I/O data transfers are desired. This bit is read-only. 0 1

PL/R

DAC data is still valid. Do not overwrite. DAC data is stale. Ready for next host data write value.

Playback Left/Right Sample. This bit indicates whether the PIO playback data needed is for the right channel DAC or left channel DAC. This bit is read-only. 0 1

PU/L

Interrupt pin inactive Interrupt pin active

Right channel needed Left channel or mono

Playback Upper/Lower Byte. This bit indicates whether the PIO playback data needed is for the upper or lower byte of the channel. This bit is read-only. 0 1

Lower byte needed Upper byte needed or any 8-bit mode

SOUR

Sample Over/Underrun. This bit indicates that the most recent sample was not serviced in time and therefore either a capture overrun (COR) or playback underrun (PUR) has occurred. The bit indicates an overrun for ADC capture and an underrun for DAC playback. If both capture and playback are enabled, the source that set this bit can be determined by reading COR and PUR. This bit changes on a sample by sample basis. This bit is read-only.

CRDY

Capture Data Ready. The PIO Capture Data Register contains data ready for reading by the host. This bit should only be used when direct programmed I/O data transfers are desired. This bit is read-only. 0 1

CL/R

Capture Left/Right Sample. This bit indicates whether the PIO capture data waiting is for the right channel ADC or left channel ADC. This bit is read-only. 0 1

CU/L

ADC data is stale. Do not reread the information. ADC data is fresh. Ready for next host data read.

Right channel Left channel or mono

Capture Upper/Lower Byte. This bit indicates whether the PIO capture data ready is for the upper or lower byte of the channel. This bit is read-only. 0 1

Lower byte ready Upper byte ready or any 8-bit mode

The PRDY, CRDY, and INT bits of this status register can change asynchronously to host accesses. The host may access this register while the bits are transitioning. The host read may return a zero value just as these bits are changing, for example. A one value would not be read until the next host access. This register’s initial state after reset is “1100 1100.”

REV. B

–15–


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