Файл:AD1845.pdf

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AD1845 XCTL1:0

External Control. The state of these bits is reflected on the XCTL1:0 pins of the AD1845. 0 Logic LO on XCTL1:0 pins 1 Logic HI on XCTL1:0 pins

This register’s initial state after reset is “00xx xx00.” Test and Initialization Register (IXA3:0 = 11) IXA3:0

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

11

ORL1:0

Data 7 COR

PUR

ACI

DRS

ORR1

ORR0

ORL1

ORL0

Overrange Left Detect. These bits indicate the overrange on the left capture channel. These bits change on a sample-by-sample basis, and are read-only. ORL1 0 0 1 1

ORR1:0

ORR0 0 1 0 1

Less than –1 dB underrange Between –1 dB and 0 dB underrange Between 0 dB and +1 dB overrange Greater than +1 dB overrange

Data Request Status. This bit indicates the current status of the PDRQ and CDRQ pins of the AD1845. 0 1

ACI

Less than –1 dB underrange Between –1 dB and 0 dB underrange Between 0 dB and +1 dB overrange Greater than +1 dB overrange

Overrange Right Detect. These bits indicate the overrange on the right capture channel. These bits change on a sample-by-sample basis, and are read-only. ORR1 0 0 1 1

DRS

ORL0 0 1 0 1

CDRQ and PDRQ are presently inactive (LO) CDRQ or PDRQ are presently active (HI)

Autocalibrate-In-Progress. This bit indicates the state of autocalibration or a recent exit from Mode Change Enable (MCE). This bit is read-only. 0 1

Autocalibration is not in progress Autocalibration is in progress or MCE was exited within the last 128 sample periods

PUR

Playback Underrun. For MODE1 operation, this bit is set when playback data has not arrived from the host within one sample to be played. As a result, a midscale value will be sent to the DACs. This bit changes on a sample by sample basis. When MODE2 is enabled, this bit is set when the playback FIFO is empty and after the next valid sample has been played back. If this condition exists, DACZ determines the DAC playback value.

COR

Capture Overrun. For MODE1 operation, this bit is set when the capture data has not been read by the host before the next sample arrives. The sample being read will not be overwritten by the new sample. The new sample will be ignored. This bit changes on a sample by sample basis. In MODE2, COR is set when the capture FIFO is full and an additional sample has been captured.

The occurrence of a PUR and/or COR is designated in the Status Register’s Sample Overrun/Underrun (SOUR) bit. The SOUR bit is the logical OR of the COR and PUR bits. This enables a polling host CPU to detect an overrun/underrun condition while checking other status bits. This register’s initial state after reset is “0000 0000.”

REV. B

–21–


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