AD1845 Miscellaneous Control Register (IXA3:0 = 12) IXA3:0
AD1845 Revision ID. These four bits define the revision level of the AD1845. The AD1845 will have ID = “1010.” These bits are read-only.
Parallel Interface Bus Transceiver Current Buffer Drive. The AD1845 can be programmed to provide a current drive of 16 mA or 8 mA. 0 1
16 mA current drive. 8 mA current drive.
Reserved for future expansion. Always write 0s to these bits.
When the AD1845 is initialized, the MODE2 bit is set to 0, LO, and the AD1845 is register set compatible with the AD1848 and the AD1846. Setting the MODE2 bit to 1, HI, enables access to the indirect registers 16 through 31 which controls the AD1845 Expanded Mode of operation. 0 1
MODE1: AD1848, AD1846, and CS4248 mode MODE2: AD1845 enhanced feature mode
Manufacturer ID Bit. This bit is set to 1.
This register’s initial state after reset is “10x0 1010.” Digital Mix/Attenuation Control Register (IXA3:0 = 13) IXA3:0
Data 7 DMA5
Digital Mix Enable. This bit will enable the digital mix of the ADC’s output with the DAC’s input. When enabled, the data from the ADCs are digitally mixed with other data being delivered to the DACs regardless of whether or not playback is enabled (PEN = 1). If capture is enabled (CEN = 1) and there is a capture overrun (COR), then the last sample captured before overrun will be used for the digital mix. If playback is enabled (PEN = 1) and there is a playback underrun (PUR), then a midscale zero will be added to the digital mix data if DACZ = 1, otherwise, the last valid sample will be repeated. 0 1
Digital mix disabled (muted) Digital mix enabled
Reserved for future expansion. Always write a zero to this bit.
Digital Mix Attenuation. These bits determine the attenuation of the ADC data that is mixed with the DAC input. Each attenuate step is –1.5 dB ranging from 0 dB to –94.5 dB.
This register’s initial state after reset is “0000 00x0.” DMA Playback Base Count Registers (IXA3:0 = 14 & 15)
The DMA Base Count Registers in the AD1845 simplify integration of the AD1845 in ISA systems. The ISA DMA controller requires an external count mechanism to notify the host CPU via interrupt of a full DMA buffer. The programmable DMA Base Count Registers will allow such interrupts to occur. The Base Count Registers contain the number of sample periods which will occur before an interrupt is generated on the interrupt (INT) pin. To load, first write a value to the Lower Base Count Register. Writing a value to the Upper Base Register will cause both Base Count Registers to load into the Current Count Register. Once AD1845 transfers are enabled, each sample period the Current Count Register will decrement until zero count is reached. The next sample period after zero will generate the interrupt and reload the Current Count Register with the values in the Base Count Registers. The interrupt is cleared by a write to the Status Register. The Host Interrupt Pin (INT) will go HI during the sample period in which the Current Count Register underflows. When using the AD1845 in MODE1 (AD1848 compatible), the Current Count Register is decremented every sample period when either the PEN or CEN bit is enabled. The Current Count Register is decremented in both PIO and DMA data transfer modes. By enabling MODE2, the AD1845 Expanded Mode, the playback counter is only decremented when a playback DMA occurs.