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AD1845 Upper Base Count Register (IXA3:0 = 14) IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

14

UB7

UB6

UB5

UB4

UB3

UB2

UB1

UB0

UB7:0

Upper Base Count. This byte is the upper byte of the base count register containing the eight most significant bits of the 16-bit base register. Reads from this register return the same value which was written. The current count contained in the counters can not be read.

This register’s initial state after reset is “ 0000 0000.” Lower Base Count Register (IXA3:0 = 15) IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

15

LB7

LB6

LB5

LB4

LB3

LB2

LB1

LB0

LB7:0

Lower Base Count. This byte is the lower byte of the base count register containing the eight least significant bits of the 16-bit base register. Reads from this register return the same value which was written. The current count contained in the counters cannot be read.

This register’s initial state after reset is “0000 0000.” Expanded Modes (MODE2 = 1)

The following registers are enabled when the AD1845 is operating in MODE2 only. Alternate Feature Enable/Left MIC Input Control Register (IXA3:0 = 16) IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

16

OL

TE

LMG4

LMG3

LMG2

LMG1

LMG0

DACZ

DACZ

DAC Zero. When an underrun error occurs, this bit will force the DAC output to midscale. 0 1

Output previous valid sample Output to midscale value

LMG4:0

Left MIC Gain. The least significant bit of this gain/attenuate select represents 1.5 dB. LMG4:0 = 0 produces a +12 dB gain. LMG4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 dB. See Figure 10.

TE

Timer Enable. Setting this bit enables the 16-bit programmable timer (see Registers 20 and 21). When the timer is enabled, the timer count is reloaded, and interrupts are generated at specified periods on the INT pin.

OL

Output Level. This bit sets the analog output level. The line output level may be attenuated by 3 dB. 0 1

Full scale of 2.0 V p (–3 dB) Full scale of 2.8 V p (0 dB)

This register’s initial state after reset is “0001 0001.” MIC Mix Enable/Right MIC Input Control Register (IXA3:0 = 17) IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

17

LMME

RMME

RMG4

RMG3

RMG2

RMG1

RMG0

res

res

Reserved for future expansion. Always write zero to this bit.

RMG4:0

Right MIC Gain. The least significant bit of this gain/attenuate select represents 1.5 dB. RMG4:0 = 0 produces a +12 dB gain. RMG4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 dB. See Figure 10.

RMME

Right MIC Mix Enable. Setting this bit enables the right microphone input to be mixed with the DAC output on R_OUT.

LMME

Left MIC Mix Enable. Setting this bit enables the left microphone input to be mixed with the DAC output on L_OUT.

This register’s initial state after reset is “0001 000x.” REV. B

–23–


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