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AD1845 Capture Playback Timer Register (IXA3:0 = 24) IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

24

res

TI

CI

PI

CU

CO

PO

PU

PU PO

Playback Underrun. This bit is set when the DAC runs out of data and a sample has been missed. Playback Overrun. This bit is set when the host tries to write data into the FIFO and the write was ignored because the FIFO was full. CO Capture Overrun. This bit is set when the ADC has a sample to load into the FIFO, and the data was ignored because the capture FIFO was full. CU Capture Underrun. This bit is set when the host attempts to read from the capture FIFO when it is empty. Under these circumstances, the last valid byte is sent to the host. PI Playback Interrupt. This bit indicates that there is an interrupt pending from the playback DMA count registers. CI Capture Interrupt. This bit indicates that there is an interrupt pending from the capture DMA count registers. TI Timer Interrupt. This bit indicates that there is an interrupt pending from the timer count registers. res Reserved for future expansion. Always write zero to this bit. This register’s initial state after reset is “x000 0000.” Revision ID Register (IXA3:0 = 25) IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

25

V2

V1

V0

res

res

CID2

CID1

CID0

V2:0 res CID2:0

Version Number. Indicates the version of the AD1845. Reserved for future expansion. Always write zeros to these bits. Chip ID Number.

This register’s initial state after reset is “100x x000.” Mono Control Registers (IXA3:0 = 26) IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

26

MIM

MOM

res

res

MIA3

MIA2

MIA1

MIA0

MIA3:0

Mono Input Attenuation. The least significant bit represents 3.0 dB attenuation. See Figure 11 to determine the attenuation. res Reserved for future expansion. Always write zeros to these bits. MOM Mono Output Mute. M_OUT is muted by setting MOM to 1. 0 Mono output not muted 1 Mono output muted MIM Mono Input Mute. M_IN is muted by setting MIM to 1. 0 Mono input not muted 1 Mono input muted This register’s initial state after reset is “00xx 0011.”

–26–

REV. B


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