AD1845 DIRECT MEMORY ACCESS (DMA) TRANSFERS
The second type of bus cycle supported by the AD1845 are DMA transfers. Both dual channel and single channel DMA operations are supported. To enable Playback DMA transfers, playback enable (PEN) must be set and PPIO cleared. To enable Capture DMA transfers, capture enable (CEN) must be set and CPIO cleared. During DMA transfers, the AD1845 asserts HI the Capture Data Request (CDRQ) or the Playback Data Request (PDRQ) followed by the host’s asserting LO the DMA Capture Data Acknowledge (CDAK) or Playback Data Acknowledge (PDAK), respectively. The host’s asserted Acknowledge CDRQ/PDRQ OUTPUTS
tSTW RD INPUT
tRDDV DATA7:0 OUTPUTS
Figure 18. Control Register/PIO Read Cycle
To avoid confusion of the origin of a request when switching between playback and capture in Single-Channel DMA mode, both CEN and PEN should be disabled and all pending requests serviced before enabling the alternative enable bit.
Switching between playback and capture in Single-Channel DMA mode does not require changing the PPIO and CPIO bits or passing through the Mode Change Enable state except for initial setup. For setup, assign zeros to both PPIO and CPIO. This configures both playback and capture for DMA. Following setup, switching between playback and capture can be effected entirely by setting and clearing the PEN and CEN control bits, a technique which avoids having to enter Mode Change Enable.
tDBDL DBEN OUTPUT DBDIR OUTPUT
tSTW WR INPUT
tWDSU DATA7:0 INPUTS
Single-Channel DMA mode allows the AD1845 to be used in systems with only a single DMA channel. It is enabled by setting the SDC bit in the Interface Configuration Register. All captures and playbacks take place on the playback channel. Obviously, the AD1845 cannot perform a simultaneous capture and playback in Single-Channel DMA mode.
Playback and capture are distinguished in Single-Channel DMA mode by the state of the playback enable (PEN) or capture enable (CEN) control bits. If both PEN and CEN are set in Single-Channel DMA mode, playback will be presumed.
Playback will occur in Single-Channel DMA mode exactly as it does in Two-Channel mode. Capture, however, is diverted to the playback channel which means that the capture data request occurs on the PDRQ pin and the capture data acknowledge must be received on the PDAK pin. The CDRQ pin will remain inactive LO. Any inputs to CDAK will be ignored.
DBEN & DBDIR OUTPUTS
DMA transfers may be independently aborted by resetting the Capture Enable (CEN) and/or Playback Enable (PEN) bits in the Interface Configuration Register. The current capture sample transfer will be completed if a capture DMA is terminated. The current playback sample transfer must be completed if a playback DMA is terminated. If CDRQ and/or PDRQ are asserted HI while the host is resetting CEN and/or PEN, the request must be acknowledged. The host must assert CDAK and/or PDAK LO and complete a final sample transfer.
The AD1845 is designed to support full duplex DMA operation by allowing simultaneous capture and playback. The DualChannel DMA feature enables playback and capture DMA requests and acknowledges to occur on separate DMA channels. Capture and playback are enabled and set for DMA transfers. In addition, Dual-Channel DMA must be set (SDC = 0). It is not necessary to enter MCE (Mode Change Enable) to change PEN and CEN (Playback and Capture Enable).
Figure 19. Control Register/PIO Write Cycle
signals cause the AD1845 to perform DMA transfers. The input address lines, ADR1:0, are ignored. Data is transferred between the proper internal sample registers. The read strobe (RD) and write strobe (WR) delimit valid data for DMA transfers. Chip select (CS) is a “don’t care”; its state is ignored by the AD1845.
The AD1845 may assert the Data Request signals, CDRQ and PDRQ, at any time. Once asserted, these signals will remain active HI until the corresponding DMA cycle occurs with the host’s Data Acknowledge signals. The Data Request signals will be deasserted after the falling edge of the final RD or WR strobe in the transfer of a sample, which typically consists of multiple bytes. See “Data Ordering” above for a definition of “sample.”
Below, timing parameters are shown for 8-Bit Mono Sample Read/Capture and Write/Playback DMA transfers in Figures 20 and 21. The same timing parameters apply to multi-byte transfers. The relationship between timing signals is shown in Figures 22 and 23. The Host Interrupt Pin (INT) will go HI after a sample transfer in which the Current Count Register underflows.