Файл:AD1845.pdf

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AD1845 DMA Interrupt

ISA BUS BCLK CDRQ OUTPUT

tDRHD tDKSU

CDAK INPUT

tDKHDb

tDBDL DBEN & DBDIR OUTPUTS

tSTW RD INPUT

tDHD1

tRDDV DATA7:0 OUTPUTS

Figure 20. 8-Bit Mono DMA Read/Capture Cycle ISA BUS BCLK PDRQ OUTPUT

tDKSU

tDRHD

PDAK INPUT

tDKHDa

tDSDL DBEN OUTPUT DBDIR OUTPUT

Writing to the internal 16-bit Base Count Register sets up the count value for the number of samples to be transferred. Note that the number of bytes transferred for a given count will be a function of the selected global data format. The internal Current Count Register is updated with the current contents of the Upper and Lower Base Count Registers when a write occurs to the Upper Base Count Register. The Current Count Register cannot be read by the host. Reading the Base Count Registers will only read back the initialization values written to them. The Current Count Register decrements by one after every sample transferred. An interrupt event is generated after the Current Count Register is zero and an additional playback sample is transferred. The INT bit in the Status Register always reflects the current internal interrupt state defined above. The external INT pin will only go active HI if the Interrupt Enable (wIEN) bit in the Interface Configuration Register is set. If the IEN bit is zero, the external INT pin will always stay LO, even though the Status Register’s INT bit may be set. POWER UP AND RESET

HI

tSTW WR INPUT

tDHD2 tWDSU

DATA7:0 OUTPUTS

Figure 21. 8-Bit Mono DMA Write/Playback Cycle ISA BUS BCLK

Upon power-up the AD1845 enters the Mode Change Enable (MCE) state. In the default condition, the AD1845 expects to receive a 24.576 MHz input clock source. To change the selection of the current or default input clock source, follow the steps listed below:

CDRQ /PDRQ OUTPUTS CDAK/PDAK INPUTS

The PWRDWN and RESET pin should be held in the active LO state when power is first applied to the AD1845. The AD1845’s initialization commences when PWRDWN and RESET have both been deasserted (HI). While initializing, the AD1845 ignores all writes and all reads will yield “1000 0000 (80h).” At the conclusion of initialization, all registers will be set to their default values as listed in Figure 5. The conclusion of the initialization period, after approximately 512 ms, can be detected by polling the index register for some value other than “1000 0000 (80h).”

tBWDN

RD OR WR INPUTS

• Wait for the AD1845 to initialize. RIGHT/ HIGH BYTE

LEFT/ LOW BYTE

DATA7:0

Figure 22. 8-Bit Stereo or 16-Bit Mono DMA Cycle

• Set the MODE2 bit to 1. • Enter the MCE state, write to the Crystal/Clock Input Frequency Select bits (XFS2:0) to select the desired frequency. • The AD1845 will now resynchronize its internal states to the new clock. Writes to the AD1845 will be ignored. Poll the index register for some value other than “1000 0000 (80h).”

ISA BUS BCLK CDRQ /PDRQ OUTPUTS

• Clear the MCE bit.

CDAK/PDAK INPUTS

tBWDN RD OR WR INPUTS

DATA7:0

LOW BYTE LEFT SAMPLE

HIGH BYTE

LOW BYTE

HIGH BYTE RIGHT SAMPLE

Figure 23. 16-Bit Stereo DMA Interrupt

REV. B

–31–


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