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AD1845 • Set to desired gain/attenuation values, and unmute DAC outputs (if muted).

AUTOCALIBRATION

The AD1845 calibrates the ADCs and DACs for greater accuracy by minimizing dc offsets. Upon power up or after RESET, the AD1845 automatically performs an autocalibration making it unnecessary to perform an autocalibration during normal operation. However, autocalibration can occur when the AD1845 returns from the Mode Change Enable state and the ACAL bit in the Interface Configuration register has been set. If the ACAL bit is not set, the RAM normally containing ADC and DAC offset compensations will be saved, retaining the offsets of the most recent autocalibration.

Alternatively, the AD1845 can be programmed to change the sample rate selection “on the fly” without entering the Mode Change Enable Sequence. The following sequence applies to the AD1845 operating in MODE1 or MODE2.

The completion of autocalibration can be determined by polling the Autocalibrate-In-Progress (ACI) bit in the Test and Initialization Register, which will be set during autocalibration. Transfers enabled during autocalibration do not begin until the completion of autocalibration. The following summarizes the procedure for autocalibration: • Set the Mode Change Enable (MCE) bit. • Set the Autocalibration (ACAL) bit. • Clear the Mode Change Enable (MCE) bit. • The Autocalibrate-In-Progress (ACI) bit will transition from LO to HI within five sample periods. It will remain HI for 384 sample periods. Poll the ACI bit until it transitions from HI to LO. • Set desired gain/attenuation/mute and digital mix values. During the autocalibration sequence, data output from the ADCs is meaningless. Inputs to the DACs are ignored. Even if the user specified the muting of all analog outputs, near the end of the autocalibration sequence, dc analog outputs very close to VREF will be produced at the line output. CHANGING SAMPLE RATES

In MODE1 the AD1845 can change sample rates by entering the Mode Change Enable state or writing directly to the Clock and Data Format Register. In MODE2, the AD1845 changes sample rates by writing directly to the Upper and Lower Frequency Select Register. Please refer to the following examples for changing the sample rate. To change the selection of the current sample rate by entering the Mode Change Enable state requires the sequence which is summarized as follows (this is the same sequence used by the AD1848, AD1846, CS4248, and CS4231): • Set the Mode Change Enable (MCE) bit. • In a single write cycle, change the Clock Frequency Divide Select (CFS2:0) and/or the Clock Source Select (CSS). • The AD1845 now needs to resynchronize its internal states to the new clock. Writes to the AD1845 will be ignored. Reads will produce “1000 0000 (80h)” until the resynchronization is complete. Poll the Index Register until something other than this value is returned. • Clear the Mode Change Enable (MCE) bit. • If ACAL is set, follow the procedure described in “Autocalibration” above. • Wait 128 sample cycles or poll the ACI bit until it transitions LO.

REV. B

• In a single write cycle, change the Clock Frequency Divide Select (CFS2:0) and/or the Clock Source Select (CSS). For compatibility reasons, the AD1845 will send out “1000 0000 (80h)” for approximately 200 µs. Even this short wait can be disabled by setting the INITD bit. When the INITD bit is set, the AD1845 is ready immediately after changing the sample rate using CFS and CSS. • The AD1845 now needs to resynchronize its internal states to the new clock. Writes to the AD1845 will be ignored. Reads will produce “1000 0000 (80h)” until the resynchronization is complete. Poll the Index Register until something other than this value is returned. • Set to desired gain/attenuation values, and unmute DAC outputs (if muted). In the Expanded Mode, MODE2, the AD1845 can be programmed to change the sample rate selection in 1 Hz increments “on the fly” and without entering the Mode Change Enable Sequence. The following sequence applies to the AD1845 in MODE2 only: • Enable the Frequency Select Register by setting FREN to 1. • Change the Lower and Upper Frequency Select Register, FU7:0 and FL7:0. APPLICATIONS CIRCUITS

The AD1845 Stereo Codec has been designed to require a minimum of external circuitry. The recommended circuits are shown in Figures 25 through 33. See Figure 1 for an illustration of the connection between the AD1845 SoundPort Codec and the Industry Standard Architecture (ISA) computer bus, also known as the “PC-AT bus.” Note that the 74_245 transceiver receives its enable and direction signals directly from the Codec. Analog Devices recommends using the “slowest” 74_245 adequately fast to meet all AD1845 and computer bus timing and drive requirements. So doing will minimize switching transients of the 74_245. This in turn will minimize the digital feed through effects of the transceiver when driving the AD1845, which can cause the audio noise floor to rise. In most applications, the 74_245 can be omitted and the AD1845 connected directly ISA bus taking advantage of the AD1845’s built-in 16 mA drivers. Industry-standard compact disc “line-levels” are 2 V rms centered around analog ground. (For other audio equipment, “line level” is much more loosely defined.) The AD1845 SoundPort is a +5 V only powered device. Line level voltage swings for the AD1845 are defined to be 1 V rms for a sine wave ADC input and user selectable 0.707 V rms or 1 V rms for a sine wave DAC output. Thus, 2 V rms input analog signals must be attenuated and either centered around the reference voltage intermediate between 0 V and +5 V or ac coupled. The VREF pin will be at this intermediate voltage, nominally 2.25 V. It has limited drive but can be used as a voltage datum to an op amp input. Note,

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