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AD607 Bias System

USING THE AD607

The AD607 operates from a single supply, VP, usually of 3 V, at a typical supply current of 8.5 mA at midgain and T = 27°C, corresponding to a power consumption of 25 mW. Any voltage from 2.7 V to 5.5 V may be used.

In this section, we will focus on a few areas of special importance and include a few general application tips. As is true of any wideband high gain component, great care is needed in PC board layout. The location of the particular grounding points must be considered with due regard to possibility of unwanted signal coupling, particularly from IFOP to RFHI or IFHI or both.

The bias system includes a fast-acting active-high CMOScompatible power-up switch, allowing the part to idle at 550 µA when disabled. Biasing is proportional-to-absolutemperature (PTAT) to ensure stable gain with temperature. An independent regulator generates a voltage at the midpoint of the supply (VP/2) which appears at the VMID pin, at a low impedance. This voltage does not shut down, ensuring that the major signal interfaces (e.g., mixer-to-IF and IF-to-demodulators) remain biased at all times, thus minimizing transient disturbances at power-up and allowing the use of substantial decoupling capacitors on this node. The quiescent consumption of this regulator is included in the idling current. VPOS

AD607

50kΩ FDIN EXTERNAL FREQUENCY REFERENCE

The I and Q output leads can include small series resistors (about 100 Ω) inside the shielded box without significant loss of performance, provided the external loading during testing is light (that is, a resistive load of more than 20 kΩ and capacitances of a few picofarads). These help to keep unwanted RF emanations out of the interior. The power supply should be connected via a throughole capacitor with a ferrite bead on both inside and outside leads. Close to the IC pins, two capacitors of different value should be used to decouple the main supply (VP) and the midpoint supply pin, VMID. Guidance on these matters is also generally included in applications schematics.

50kΩ

a. Biasing FDIN from Supply when Using External Frequency Reference

Gain Distribution

As in all receivers, the most critical decisions in effectively using the AD607 relate to the partitioning of gain between the various subsections (Mixer, IF Amplifier, Demodulators) and the placement of filters, so as to achieve the highest overall signal-tonoise ratio and lowest intermodulation distortion.

AD607 FDIN EXTERNAL FREQUENCY REFERENCE

The high sensitivity of the AD607 leads to the possibility that unwanted local EM signals may have an effect on the performance. During system development, carefully-shielded test assemblies should be used. The best solution is to use a fullyenclosed box enclosing all components, with the minimum number of needed signal connectors (RF, LO, I and Q outputs) in miniature coax form.

50kΩ VMID

Figure 42 shows the main RF/IF signal path at maximum and minimum signal levels.

CBYPASS

b. Biasing FDIN from VMID when Using External Frequency Reference Figure 41. Suggested Methods for Biasing Pin FDIN at VP/2 I ±54mV MAX INPUT

±1.3V MAX OUTPUT MXOP

RFHI

±54mV MAX INPUT

±560mV MAX OUTPUT IFOP

IFHI

IF BPF

LOIP CONSTANT –16dBm (±50mV)

330Ω

330Ω

(TYPICAL IMPEDANCE)

±154mV MAX INPUT

IOUT

DMIP QOUT

IF BPF

(VMID)

Q

(LOCATION OF OPTIONAL SECOND IF FILTER)

Figure 42. Signal Levels for Minimum and Maximum Gain

REV. 0

–17–

±1.23V MAX OUTPUT


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