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AD767 Ref Out, VOUT (Pins 6, 9) . . . Indefinite short to power ground Momentary Short to VCC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW

ABSOLUTE MAXIMUM RATINGS*

VCC to Power Ground . . . . . . . . . . . . . . . . . . . . .0 V to +18 V VEE to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to –18 V Digital Inputs (Pins 11, 13–24) to Power Ground . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . . . ± 12 V Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . . ± 12 V 10 V Span R to Reference Ground . . . . . . . . . . . . . . . . . ± 12 V 20 V Span R to Reference Ground . . . . . . . . . . . . . . . . . ± 24 V

• Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Symbol

Data Valid to End of CS (–25°C to +85°C) (–55°C to +125°C)

40 60 90

– – –

– – –

ns ns ns

tDH

Data Hold Tiıne (–25°C to +85°C) (–55°C to +125°C)

10 10 20

– – –

– – –

ns ns ns

tCS

CS Pulse Width (–25°C to +85°C) (–55°C to +125°C)

40 60 90

– – –

– – –

ns ns ns

tSETT

(All Models, TA = 25°C, VCC = +12 V or +15 V, VEE = –12 V or –15 V)

Min Typ Max

tDS

TIMING SPECIFICATIONS

Parameter

Output Voltage Settling Time* –

2

4

µs

• tSETT is measured referenced to the leading edge of t CS. If tCS > tDS, then tSETT is measured referenced to the beginning of Data Valid.

PIN CONFIGURATION DIP

PLCC

ORDERING GUIDE

Model1

Package

Linearity Temperature Error Max Range ؇C TMIN–TMAX

Gain T.C. Max ppm/؇C

AD767JN AD767JP AD767KN AD767KP AD767AD AD767BD AD767SD/ 883B AD767A Chips

Plastic DIP PLCC Plastic DIP PLCC Ceramic DIP Ceramic DIP

0 to +70 0 to +70 0 to +70 0 to +70 –25 to +85 –25 to +85

± 1 LSB ± 1 LSB ± 1/2 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB

30 30 15 15 30 15

Ceramic DIP

–55 to +125

Note 2

Note 2

N/A

–25 to +85

± 1 LSB

30

NOTES 1 D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier. 2 For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current AD767/883B data sheet.

REV. A

–3–