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AD767

Figure 5e. Fine-Scale Settling, CF = 20 pF

Figure 6. 68000 – AD767 Interface

DIGITAL INPUT CONSIDERATIONS

8086 – AD767 INTERFACE

The threshold of the digital input circuitry is set at 1.4 volts and does not change with supply voltage. Thus the AD767 digital interface may be driven with any of the popular types of 5 volt logic.

Interfacing the AD767 to the 8086 16-bit microprocessor requires a minimal amount of external components. A 10 MHz 8086, for example, generates a 165 ns low write pulse which may be gated with a decoded address to provide CS for the AD767. As WR returns high valid data is latched into the DAC. See Figure 7.

A good engineering practice is to connect unused inputs to power ground to improve noise immunity. Unconnected data and control inputs will float to logic 0 if left open. The low digital input current of the AD767 eliminates the need for buffer/drivers required by many monolithic converters using bipolar technology. A single low-power Schottky gate, for example, will drive several AD767s when connected to a common bus. INPUT CODING

The AD767 uses positive-true binary input coding. Logic “1” is represented by an input voltage greater than 2.0 V, and logic “0” is defined as an input voltage less than 0.8 V. Unipolar coding is straight binary, where all zeroes (000H) on the data inputs yields a zero analog output and all ones (FFFH) yields an analog output 1 LSB below full scale.

Figure 7. 8086 – AD767 Interface TMS32010 – AD767 INTERFACE

The high-speed digital interface of the AD767 facilitates its use with the TMS32010 microprocessor at speeds up to 20 MHz. In the three multiplexed LSBs of the address bus, PA2 – PA0 are decoded as a port address and OR’ed with the low write enable to generate CS for the DAC. A simple OUT xx,y instruction will output the data word stored in memory location xx to any one of eight port locations y.

Bipolar coding is offset binary, where an input code of 000H yields a minus full-scale output, an input of FFFH yields an output 1 LSB below positive full scale, and zero occurs for an input code with only the MSB on (800H). The AD767 can be used with twos complement input coding if an inverter is used on the MSB (DB11). MICROPROCESSOR INTERFACE

The AD767, with its 40 ns minimum CS pulse width, may be easily interfaced to any of today’s high-speed microprocessors. The 12-bit single buffered input register will accept 12-bit parallel data from processors such as the 68000, 8086, TMS320 series, and the Analog Devices ADSP-2100. Several illustrative examples follow. 68000 – AD767 INTERFACE

Figure 6 illustrates the AD767 interface to a 68000 microprocessor. An active low decoded address is OR’ed with the processor’s R/W signal to provide CS and latch data into the AD767. Later in the bus cycle the processor issues the upper (UDS) and lower (LDS) data strobes which are gated with the decoded address to provide DTACK and terminate the bus cycle. As shown, this interface will support a 12.5 MHz 68000 system.

REV. A

Figure 8. TMS32010 – AD767 Interface TMS32020 – AD767 INTERFACE

Interfacing the AD767 to the TMS32020 microprocessor is easily achieved by using the TMS32020 I/O port capability. The IS signal distinguishes the I/O address space from the local program/data memory space and is used to enable a 74LS138 decoder. The decoded port address is then gated with the R/W and STRB signals to provide the AD767 CS. –7–


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