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AD7874 MICROPROCESSOR INTERFACING

TIMER

The AD7874 high speed bus timing allows direct interfacing to DSP processors as well as modern 16-bit microprocessors. Suitable microprocessor interfaces are shown in Figures 12 through 16.

PA2 ADDRESS BUS PA0

ADDR DECODE

Figure 12 shows an interface between the AD7874 and the ADSP-2100. Conversion is initiated using a timer which allows very accurate control of the sampling instant on all four channels. The AD7874 INT line provides an interrupt to the ADSP2100 when conversion is completed on all four channels. The four conversion results can then be read from the AD7874 using four successive reads to the same memory address. The following instruction reads one of the four results (this instruction is repeated four times to read all four results in sequence): MR0 = DM(ADC)

MEN

INT

INT

DEN

RD DB11 DB0

D15 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY

Figure 13. AD7874–TMS32010 Interface

TIMER

AD7874–TMS320C25 Interface

DMA0

Figure 14 shows an interface between the AD7874 and the TMS320C25. As with the two previous interfaces, conversion is initiated with a timer and the processor is interrupted when the conversion sequence is completed. The TMS320C25 does not have a separate RD output to drive the AD7874 RD input directly. This has to be generated from the processor STRB and R/W outputs with the addition of some logic gates. The RD signal is OR-gated with the MSC signal to provide the one WAIT state required in the read cycle for correct interface timing. Conversion results are read from the AD7874 using the following instruction: IN D,ADC

CONVST

DMS

AD7874*

D0

ADDRESS BUS

ADDR DECODE

CS

TMS32010

where MR0 is the ADSP-2100 MR0 register and ADC is the AD7874 address. DMA13

CONVST

EN

AD7874–ADSP-2100 Interface

CS

EN

AD7874*

ADSP-2100 (ADSP-2101/ ADSP-2102) IRQn

INT

DMRD (RD)

RD DB11 DB0

where D is Data Memory address and ADC is the AD7874 address.

DMD15 DATA BUS DMD0 * ADDITIONAL PINS OMITTED FOR CLARITY

TIMER A15

Figure 12. AD7874–ADSP-2100 Interface

ADDRESS BUS

A0

AD7874–ADSP-2101/ADSP-2102 Interface

The interface outlined in Figure 12 also forms the basis for an interface between the AD7874 and the ADSP-2101/ADSP-2102. The READ line of the ADSP-2101/ADSP-2102 is labeled RD. In this interface, the RD pulse width of the processor can be programmed using the Data Memory Wait State Control Register. The instruction used to read one of the four results is as outlined for the ADSP-2100.

ADDR DECODE IS

CONVST

EN

CS

AD7874*

TMS320C25

INT

INTn STRB

AD7874–TMS32010 Interface

RD

R/W

An interface between the AD7874 and the TMS32010 is shown in Figure 13. Once again the conversion is initiated using an external timer and the TMS32010 is interrupted when all four conversions have been completed. The following instruction is used to read the conversion results from the AD7874: IN D,ADC

READY DB11

MSC

DB0

D15 DATA BUS D0

where D is Data Memory address and ADC is the AD7874 address.

  • ADDITIONAL PINS OMITTED FOR CLARITY

Figure 14. AD7874–TMS320C25 Interface

–10–

REV. C


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