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AD7874 MULTIPLE AD7874s

Figure 18 shows a system where a number of AD7874s can be configured to handle multiple input channels. This type of configuration is common in applications such as sonar, radar, etc. The AD7874 is specified with maximum and minimum limits on aperture delay. This means that the user knows the maximum difference in the sampling instant between all channels. This allows the user to maintain relative phase information between the different channels. A common read signal from the microprocessor drives the RD input of all AD7874s. Each AD7874 is designated a unique address selected by the address decoder. The reference output of AD7874 number 1 is used to drive the reference input of all other AD7874s in the circuit shown in Figure 18. One REF OUT pin can drive several AD7874 REF IN pins. Alternatively, an external or system reference can be used to drive all REF IN inputs. A common reference ensures good full-scale tracking between all channels.

RD

VCH3

AD7874(1)

VCH4

Microprocessor connections to the board are made via a 26contact IDC connector, SKT8, the pinout for which is shown in Figure 19. This connector contains all data, control and status signals of the AD7874 (with the exception of the CLK input and the CONVST input which are provided via SKT5 and SKT7, respectively). It also contains decoded R/W and STRB inputs which are necessary for TMS32020 interfacing (and also for 68000 interfacing although pin labels on the 68000 are different). Note that the AD7874 CS input must be decoded prior to the AD7874 evaluation board. SKT1, SKT2, SKT3 and SKT4 provide the inputs for VIN1, VIN2, VIN3, VIN4 respectively. Assuming LK1 to LK4 are in place, these input signals are fed to four buffer amplifiers, IC1, before being applied to the AD7874. The use of an external clock source is optional; there is a shorting plug (LK5) on the AD7874 CLK input which must be connected to either –5 V (for the ADCs own internal clock) or to SKT5. SKT6 and SKT7 provide the reference and CONVST inputs respectively. Shorting plug LK6 provides the option of using the external reference or the ADCs own internal reference.

VCH1 VCH2

the input signal connects to the buffer amplifier driving the analog input of the ADC. If the shorting plug is omitted, a wire link can be used to connect the input signal to the PCB component grid.

RD

CS REF OUT

R/W

VCH8

6

N/C

7

8

INT

N/C

9

10

N/C

DB10

11

12

DB11

13

14

DB9

15

16

DB7

17

18

DB5

DB2

19

20

DB3

DB0

21

22

DB1

+ 5V

23

24

+ 5V

GND

ADDRESS

5

DB4

ADDRESS DECODE

N/C

DB6

CS

4

DB8

VCH7

AD7874(2)

3

N/C

RD

STRB

CS

VCH6

2

RD

VCH5

1

25

26

GND

REF IN

REF IN VCHm VCHm+1

RD

AD7874(n)

VCHm+2 VCHm+3

CS

Figure 18. Multiple AD7874s in Multichannel System

Figure 19. SKT8, IDC Connector Pinout

DATA ACQUISITION BOARD

POWER SUPPLY CONNECTIONS

Figure 20 shows the AD7874 in a data acquisition circuit. The corresponding printed circuit board (PCB) layout and silkscreen are shown in Figures 21 to 23. A 26-contact IDC connector provides for a microprocessor connection to the board.

The PCB requires two analog power supplies and one 5 V digital supply. The analog supplies are labeled V+ and V– and the range for both supplies is 12 V to 15 V (see silkscreen in Figure 23). Connection to the 5 V digital supply is made via SKT8. The +5 V supply and the –5 V supply required by the AD7874 are generated from voltage regulators (IC3 and IC4) on the V+ and V– supplies.

A component grid is provided near the analog inputs on the PCB which may be used to provide antialiasing filters for the analog input channels or to provide signal conditioning circuitry. To facilitate this option, four shorting plugs (labeled LK1 to LK4 on the PCB) are provided on the analog inputs, one plug per input. If the shorting plug for a particular channel is used,

REV. C

–13–


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