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(VDD = +5 V, VSS = –5 V, AGND = DGND = 0 V, REF IN = +3 V, fCLK = 2.5 MHz MIN to TMAX unless otherwise noted.)

AD7874–SPECIFICATIONS external. All specifications T Parameter SAMPLE-AND-HOLD Acquisition Time2 to 0.01% Droop Rate2, 3 –3 dB Small Signal Bandwidth3 Aperture Delay2 Aperture Jitter2, 3 Aperture Delay Matching2

A Version B Version S Version Units 2 1 500 0 40 200 4

2 1 500 0 40 200 4

2 2 500 0 40 200 4

µs max mV/ms max kHz typ ns min ns max ps typ ns max

Test Conditions/Comments

VIN = 500 mV p

SAMPLE-AND-HOLD AND ADC DYNAMIC PERFORMANCE Signal-to-Noise Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion 2nd Order Terms 3rd Order Terms Channel-to-Channel Isolation2

70 –78 –78

71 –80 –80

70 –78 –78

dB min dB max dB max

–80 –80 –80

–80 –80 –80

–80 –80 –80

dB max dB max dB max

DC ACCURACY Resolution Relative Accuracy Differential Nonlinearity Positive Full-Scale Error4 Negative Full-Scale Error4 Full-Scale Error Match Bipolar Zero Error Bipolar Zero Error Match

12 ±1 ±1 ±5 ±5 5 ±5 4

12 ± 1/2 ±1 ±5 ±5 5 ±5 4

12 ±1 ±1 ±5 ±5 5 ±5 4

Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max

ANALOG INPUTS Input Voltage Range Input Current

± 10 ± 600

± 10 ± 600

± 10 ± 600

Volts µA max

REFERENCE OUTPUTS REF OUT REF OUT Error @ +25°C TMIN to TMAX REF OUT Temperature Coefficient Reference Load Change

3 ± 0.33 ±1 ± 35 ±1

3 ± 0.33 ±1 ± 35 ±1

3 ± 0.33 ±1 ± 35 ±2

V nom % max % max ppm/°C typ mV max

REFERENCE INPUT Input Voltage Range Input Current Input Capacitance3

2.85/3.15 ±1 10

2.85/3.15 ±1 10

2.85/3.15 ±1 10

V min/V max 3 V ± 5% µA max pF max

LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3

2.4 0.8 ± 10 10

2.4 0.8 ± 10 10

2.4 0.8 ± 10 10

V min V max µA max pF max

VDD = 5 V ± 5% VDD = 5 V ± 5% VIN = 0 V to VDD

4.0 0.4

4.0 0.4

4.0 0.4

V min V max

VDD = 5 V ± 5%; ISOURCE = 40 µA VDD = 5 V ± 5%; ISINK = 1–6 mA

µA max pF max

VIN = 0 V to VDD

V nom V nom mA max mA max mW max

± 5% for Specified Performance ± 5% for Specified Performance CS = RD = CONVST = +5 V; Typically 12 mA CS = RD = CONVST = +5 V; Typically 8 mA CS = RD = CONVST = +5 V; Typically 100 mW

LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL DB0–DB11 Floating-State Leakage Current Floating-State Output Capacitance Output Coding POWER REQUIREMENTS VDD VSS IDD ISS Power Dissipation

± 10 10

+5 –5 18 12 150

± 10 ± 10 10 10 2s COMPLEMENT +5 –5 18 12 150

+5 –5 18 12 150

fIN = 10 kHz Sine Wave, fSAMPLE = 29 kHz fIN = 10 kHz Sine Wave, fSAMPLE = 29 kHz fIN = 10 kHz Sine Wave, fSAMPLE = 29 kHz fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 29 kHz

No Missing Codes Guaranteed Any Channel Any Channel Between Channels Any Channel Between Channels

Reference Load Current Change (0–500 µA) Reference Load Should Not Be Changed During Conversion

NOTES 1 Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C. 2 See Terminology. 3 Sample tested @ +25°C to ensure compliance. 4 Measured with respect to the REF IN voltage and includes bipolar offset error. 5 For capacitive loads greater than 50 pF a series resistor is required. Specifications subject to change without notice.

–2–

REV. C


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