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AD7874 (VDD = +5 V ؎ 5%, VSS = –5 V ؎ 5%, AGND = DGND = O V, tCLK = 2.5 MHz external unless

TIMING CHARACTERISTICS1 otherwise noted.) Parameter

A, B Versions

S Version

Units

Conditions/Comments

t1 t2 t3 t4 t5 t6 2 t7 3

50 0 60 0 60 57 5 45 130 31 32.5 31 35 10

50 0 70 0 60 70 5 50 150 31 32.5 31 35 10

ns min ns min ns min ns min ns max ns max ns min ns max ns min µs min µs max µs min µs max µs max

CONVST Pulse Width CS to RD Setup Time RD Pulse Width CS to RD Hold Time RD to INT Delay Data Access Time after RD Bus Relinquish Time after RD

t8 tCONV

tCLK

Delay Time between Reads CONVST to INT, External Clock CONVST to INT, External Clock CONVST to INT, Internal Clock CONVST to INT, Internal Clock Minimum Input Clock Period

NOTES 1 Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 2 t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 3 t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice. 1.6mA

ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V Digital Outputs to DGND . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C Power Dissipation (Any Package) to +75°C . . . . . . 1,000 mW Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

Figure 1. Load Circuit for Access Time

  • Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 2. Load Circuit for Bus Relinquish Time

TO OUTPUT PIN

+ 2.1V 50pF

200µA

1.6mA

TO OUTPUT PIN

+ 2.1V 50pF

200µA

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7874 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. C

–3–

WARNING! ESD SENSITIVE DEVICE


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