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AD7874 TERMINOLOGY

PIN CONFIGURATIONS

ACQUISITION TIME

Acquisition Time is the time required for the output of the track/hold amplifiers to reach their final values, within ± 1/2 LSB, after the falling edge of INT (the point at which the track/ holds return to track mode). This includes switch delay time, slewing time and settling time for a full-scale voltage change.

DIP and SOIC

VIN1

1

28 VIN4

VIN2

2

27 VIN3

VDD

3

26 VSS

INT

4

25 REF OUT

CONVST

5

24 REF IN

RD

6

23 AGND

CS

7

CLK

8

APERTURE DELAY

Aperture Delay is defined as the time required by the internal switches to disconnect the hold capacitors from the inputs. This produces an effective delay in sample timing. It is measured by applying a step input and adjusting the CONVST input position until the output code follows the step input change.

AD7874

22 DB0 (LSB) TOP VIEW (Not to Scale) 21 DB1

VDD DB11 (MSB)

19 DB3

DB10 11

APERTURE DELAY MATCHING

9 10

18 DB4

Aperture Delay Matching is the maximum deviation in aperture delays across the four on-chip track/hold amplifiers.

20 DB2

DB9 12

16 DB6

DGND 14

APERTURE JITTER

17 DB5

DB8 13

15 DB7

Aperture Jitter is the uncertainty in aperture delay caused by internal noise and variation of switching thresholds with signal level.

VIN2

VIN1

VIN3

VDD

Droop Rate is the change in the held analog voltage resulting from leakage currents.

4

3

2

1 28 27 26

VSS

DROOP RATE

INT

VIN4

LCCC

25 REF OUT

CONVST

5

CHANNEL-TO-CHANNEL ISOLATION

RD

6

Channel-to-Channel Isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale 1 kHz signal to the other three inputs. The figure given is the worst case across all four channels.

CS

7

AD7874

CLK

8

VDD

9

TOP VIEW (Not to Scale)

24 REF IN 23 AGND 22 DB0 (LSB) 21 DB1

DB11 (MSB) 10 DB10 11

SNR, THD, IMD

20 DB2 19 DB3

DB4

DB6

DB5

DB7

DGND

DB9

–4–

DB8

12 13 14 15 16 17 18

See DYNAMIC SPECIFICATIONS section.

REV. C


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