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AD7874 The first read operation to the AD7874 after conversion always accesses data from Data Register 1 (i.e., the conversion result from the VIN1 input). INT is reset high on the falling edge of RD during this first read operation. The second read always accesses data from Data Register 2 and so on. The address pointer is reset to point to Data Register 1 on the rising edge of CONVST. A read operation to the AD7874 should not be attempted during conversion. The timing diagram for the AD7874 conversion sequence is shown in Figure 7. TRACK/HOLDS GO INTO HOLD

t1 CONVST

tCONV

tACQUISITION

INT

t5 CS

t8

t2

t4 t3

RD

t6 DATA

HIGH-IMPEDANCE

t7 CH1 DATA

HIGH- CH2 DATA Z

HIGH- CH3 HIGH- CH4 DATA DATA Z Z

HIGH-Z

TIMES t2, t3, t4, t6, t7, AND t8 ARE THE SAME FOR ALL FOUR READ OPERATIONS.

Figure 7. AD7874 Timing Diagram Figure 8. AD7874 FFT Plot

AD7874 DYNAMIC SPECIFICATIONS

The AD7874 is specified and 100% tested for dynamic performance specifications as well as traditional dc specifications such as Integral and Differential Nonlinearity. These ac specifications are required for the signal processing applications such as phased array sonar, adaptive filters and spectrum analysis. These applications require information on the ADC’s effect on the spectral content of the input signal. Hence, the parameters for which the AD7874 is specified include SNR, harmonic distortion, intermodulation distortion and peak harmonics. These terms are discussed in more detail in the following sections.

Effective Number of Bits

Signal-to-Noise Ratio (SNR)

Figure 9 shows a typical plot of effective number of bits versus frequency for an AD7874BN with a sampling frequency of 29 kHz. The effective number of bits typically falls between 11.75 and 11.87 corresponding to SNR figures of 72.5 dB and 73.2 dB.

The formula given in Equation 1 relates the SNR to the number of bits. Rewriting the formula, as in Equation 2, it is possible to get a measure of performance expressed in effective number of bits (N). N=

(2)

The effective number of bits for a device can be calculated directly from its measured SNR.

SNR is the measured signal to noise ratio at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fs/2) excluding dc. SNR is dependent upon the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to noise ratio for a sine wave input is given by SNR = (6.02N + 1.76) dB

SNR − 1.76 6.02

(1)

where N is the number of bits. Thus for an ideal 12-bit converter, SNR = 74 dB. The output spectrum from the ADC is evaluated by applying a sine wave signal of very low distortion to the VIN input which is sampled at a 29 kHz sampling rate. A Fast Fourier Transform (FFT) plot is generated from which the SNR data can be obtained. Figure 8 shows a typical 2048 point FFT plot of the AD7874BN with an input signal of 10 kHz and a sampling frequency of 29 kHz. The SNR obtained from this graph is 73.2 dB. It should be noted that the harmonics are taken into account when calculating the SNR.

z

Figure 9. Effective Numbers of Bits vs. Frequency

–8–

REV. C


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