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AD790 VOUT

CIRCUIT DESCRIPTION

The AD790 possesses the overall characteristics of a standard monolithic comparator: differential inputs, high gain and a logic output. However, its function is implemented with an architecture which offers several advantages over previous comparator designs. Specifically, the output stage alleviates some of the limitations of classic “TTL” comparators and provides a symmetric output. A simplified representation of the AD790 circuitry is shown in Figure 13.

VH

VH VOH

VOL 0

+IN VOS

VLOGIC VH = HYSTERESIS VOLTAGE

+ –

A1

VOS = INPUT OFFSET VOLTAGE

Q1

+IN

2 7

VOUT

3 GND

+IN

+

– IN

OUTPUT

Av

Figure 14. Hysteresis Definitions (N, Q Package Pinout)

– A2 + GAIN STAGE

OUTPUT STAGE

hysteresis range. This built-in hysteresis allows the AD790 to avoid oscillation when an input signal slowly crosses the ground level. Q2

SUPPLY VOLTAGE CONNECTIONS GND

Figure 13. AD790 Block Diagram

The output stage takes the amplified differential input signal and converts it to a singlended logic output. The output swing is defined by the pull-up PNP and the pull-down NPN. These produce inherent rail-to-rail output levels, compatible with CMOS logic, as well as TTL, without the need for clamping to internal bias levels. Furthermore, the pull-up and pull-down levels are symmetric about the center of the supply range and are referenced off the VLOGIC supply and ground. The output stage has nearly symmetric dynamic drive capability, yielding equal rise and fall times into subsequent logic gates. Unlike classic TTL or CMOS output stages, the AD790 circuit does not exhibit large current spikes due to unwanted current flow between the output transistors. The AD790 output stage has a controlled switching scheme in which amplifiers A1 and A2 drive the output transistors in a manner designed to reduce the current flow between Q1 and Q2. This also helps minimize the disturbances feeding back to the input which can cause troublesome oscillations.

The AD790 may be operated from either single or dual supply voltages. Internally, the VLOGIC circuitry and the analog frontend of the AD790 are connected to separate supply pins. If dual supplies are used, any combination of voltages in which +VS ≥ VLOGIC – 0.5 V and –VS ≤ 0 may be chosen. For single supply operation (i.e., +VS = VLOGIC), the supply voltage can be operated between 4.5 V and 7 V. Figure 15 shows some other examples of typical supply connections possible with the AD790. BYPASSING AND GROUNDING

Although the AD790 is designed to be stable and free from oscillations, it is important to properly bypass and ground the power supplies. Ceramic 0.1 µF capacitors are recommended and should be connected directly at the AD790’s supply pins. These capacitors provide transient currents to the device during comparator switching. The AD790 has three supply voltage pins, +VS, –VS and VLOGIC. It is important to have a common ground lead on the board for the supply grounds and the GND pin of the AD790 to provide the proper return path for the supply current. LATCH OPERATION

HYSTERESIS

The AD790 has a latch function for retaining input information at the output. The comparator decision is “latched” and the output state is held when Pin 5 is brought low. As long as Pin 5 is kept low, the output remains in the high or low state, and does not respond to changing inputs. Proper capture of the input signal requires that the timing relationships shown in Figure 12 are followed. Pin 5 should be driven with CMOS or TTL logic levels.

The AD790 uses internal feedback to develop hysteresis about the input reference voltage. Figure 14 shows how the input offset voltage and hysteresis terms are defined. Input offset voltage (VOS) is the difference between the center of the hysteresis range and the ground level. This can be either positive or negative. The hysteresis voltage (VH) is one-half the width of the

The output of the AD790 will respond to the input when Pin 5 is at a high logic level. When not in use, Pin 5 should be connected to the positive logic supply. When using dual supplies, it is recommended that a 510 Ω resistor be placed in series with Pin 5 and the driving logic gate to limit input currents during power up.

The output high and low levels are well controlled values defined by VLOGIC (+5 V), ground and the transistor equivalent “Schottky” clamps and are compatible with TTL and CMOS logic requirements. The fanout of the output stage is shown in Figure 6 for standard LSTTL or HCMOS gates. Output drive behavior vs. capacitive load is shown in Figure 5.

–6–

REV. B


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