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AD8011 where R1 is the input resistance to A2/A2B, and τ1 (equal to CD × R1 × A2) is the open loop dominate time constant.

20

400 SERIES 1

370

0

IMPEDANCE

140

0

120

–40 –80

GAIN

60

–160

TO(s) 40 20

1E+05 1E+06 1E+07 FREQUENCY – Hz

1E+08

250

–80

Z I (s)

220

–100

190

–120 –140

–280 1E+09

Figure 31. Open-Loop Transimpedance Gain

Note that the ac open-loop plots in Figures 31, 32 and 33 are based on the full Spice AD8011 simulations and do not include external parasitics (see below). Nevertheless, these ac loop equations still provide a good approximation to simulated and actual performance up to the CLBW of the amplifier. Typically gmc × R1 is –4, resulting in AO(s) having a right half plane pole. In the time domain (inverse Laplace of AO) it appears as unstable, causing VO to exponentially rail out of its linear region. When the loop is closed however, the BW is greatly extended and the transimpedance gain, TO (s) “overrides” and directly controls the amplifiers stability behavior due to ZI approaching 1/2 gmf for s>>1/τ1. See Figure 32. This can be seen by the ZI (s) and AV (s) noninverting transfer equations below.   Sτ1 +1 (1 – gmc × R1) 1 – gmc × R1    ZI (s) = 2 × gmf (Sτ1 + 1)

SERIES 2

1E+04

1E+05 1E+06 1E+07 FREQUENCY – Hz

–160

1E+08

–180 1E+09

Figure 32. Open-Loop Inverting Input Impedance

–240

1E+04

–60

280

100 1E+03

–200

0 1E+03

–40

130

PHASE – Degrees

GAIN – dB Ohms

–120

80

PHASE

310

160

PHASE 100

–20

ZI (s) goes positive real and approaches 1/2 gmf as ω approaches (gmc × R1 – 1)/τ1. This results in the input resistance for the AV (s) complex term being 1/2 gmf; the parallel thermal emitter resistances of Q3/Q4. Using the computed CLBW from AV (s) above and the nominal design values for the other parameters, results in a closed loop 3 dB BW equal to the open loop corner frequency (1/2 πτ1) times 1/[G/(2 gmf × TO) + RF/TO]. For a fixed RF, the 3 dB BW is controlled by the RF/TO term for low gains and G/(2 gmf × TO) for high gains. For example, using nominal design parameters and R1 = 1 kΩ (which results in a nominal TO of 1.2 MΩ, the computed BW is 80 MHz for G = 0 (inverting I-V mode with RN removed) and 40 MHz for G = +10/–9. DRIVING CAPACITIVE LOADS

The AD8011 was designed primarily to drive nonreactive loads. If driving loads with a capacitive component is desired, best settling response is obtained by the addition of a small series resistance as shown in Figure 33. The accompanying graph shows the optimum value for RSERIES vs. capacitive load. It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of RSERIES and CL. 1kΩ

RSERIES

A (s) = V

1kΩ

G RF   RF  G  G   1 + A + TO   Sτ1 2 gmf TO + TO  + 1   O   

AD8011 RL 1kΩ

Figure 33. Driving Capacitive Load

REV. 0

PHASE – Degrees

|A2|×R1 2 sτ1+1

RESISTANCE – Ohms

and TO (s) =

340

–11–

CL


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