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AD8011 11



VS = ±5V G = +2 VIN = 200mV

9 8

RF = 750Ω





7 6 RF = 1kΩ

5 4 3 2 1

10 0







CL – pF




Figure 35. Flatness vs. Feedback

Figure 34. Recommended RSERIES vs. Capacitive Load for ≤ 30 ns Settling to 0.1% OPTIMIZING FLATNESS

As mentioned, the ac transfer equations above are based on a simplified single pole model. Due to the devices internal parasitics (primarily CP1/CP1B and CP2 in Figure 28) and external package/board parasites (partially represented in Figure 34) the computed BW, using the VO (s) equation above, typically will be lower than the AD8011’s measured small signal BW. See data sheet Bode plots. With internal parasitics included only, the BW is extended do to the complex pole pairs created primarily by CP1/CP2B and CP2 versus the single-pole assumption shown above. This results in a “design controlled” closed-loop damping factor (ζ) of nominally 0.6 resulting in the CLBW increasing by approximately 1.3× higher than the computed single pole value above for optimized external gains of +2/–1! As external noninverting gain (G) is increased, the actual closed-loop bandwidth vs. the computed single pole ac response is in closer agreement. Inverting pin and external component capacitance (designated CP) will further extend the CLBW do the closed loop zero created by CP and RNʈRF when operating in the noninverting mode. Using proper RF component and layout techniques (see layout section) this capacitance should be about 1.5 pF. This results in a further incremental BW increase of almost 2× (versus the computed value) for G = +1 decreasing and approaching its complex pole pair BW for gains approaching +6 or higher. As previously discussed, the single-pole response begins to correlate well. Note that a pole is also created by 1/2 gmf and CP which prevents the AD8011 from becoming unstable. This parasitic has the greatest effect on BW and peaking for low positive gains as the data sheet Bode plots clearly show. For inverting operation, CP has relatively much less effect on CLBW variation.

Output pin and external component capacitance (designated CL) will further extend the devices BW and can also cause peaking below and above the CLBW if too high. In the time domain, poor step settling characteristics (ringing up to about 2 GHz and excessive overshoot) can result. For high CL values greater than about 5 pF an external series “damping” resistor is recommended. See section on Settling Time vs. CL. For light loads, any output capacitance will reflect back on A2’s output (Z2 of buffer A3) as both added capacitance near the CLBW (CLBW > fT/B) and eventually negative resistance at much higher frequencies. These added effects are proportional to the load C. This reflected capacitance and negative resistance has the effect of both reducing A2/s phase margin and causing high frequency “L × C” peaking respectively. Using an external series resistor (as specified above) reduces these unwanted effects by creating a reflected zero to A2’s output which will reduce the peaking and eliminate ringing. For heavy resistive loads, relatively more Load C would be required to cause these same effects. High inductive parasitics, especially on the supplies and inverting/ noninverting inputs, can cause modulated low level RF ringing on the output in the transient domain. Again, proper RF component and board layout practices need to be observed. Relatively high parasitic lead inductance (roughly L >15 nh) can result in L × C underdamped ringing. Here L/C means all associated input pin, external component and leadframe strays including collector to substrate device capacitance. In the ac domain, this L × C resonance effect would typically not appear in the passband of the amplifier but would appear in the open loop response at frequencies well above the CLBW of the amplifier.


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