AD8011 LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8011 requires careful attention to board layout and component selection. Table I shows the recommended component values for the AD8011 and Figures 38–40 show the layout for the AD8011 evaluation board (8-pin SOIC, Gain = +2). Proper RF design techniques and low parasitic component selection are mandatory.
C1 0.01µF C2 0.01µF
The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near the input pins to reduce stray capacitance.
C4 10µF –VS
INVERTING CONFIGURATION RG
Chip capacitors should be used for supply bypassing (see Figure 37). One end should be connected to the ground plane and the other within 1/8 in. of each power pin. An additional (4.7 µF–10 µF) tantalum electrolytic capacitor should be connected in parallel.
The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance greater than 1.5 pF at the inverting input will significantly affect high speed performance when operating at low noninverting gains.
C4 10µF –VS
Figure 37. Inverting and Noninverting Configurations
Stripline design techniques should be used for long signal traces (greater than about 1 in.). These should be designed with the proper system characteristic impedance and be properly terminated at each end. Table I. Typical Bandwidth vs. Gain Setting Resistors
Small Signal –3 dB BW (MHz), VS = ± 5 V
–1 –2 –10 +1 +2 +10 +6 +6
1000 Ω 1000 Ω 499 Ω 1000 Ω 1000 Ω 422 Ω 1000 Ω 500 Ω
1000 Ω 499 Ω 49.9 Ω – 1000 Ω 47.5 Ω 200 Ω 100 Ω
52.3 Ω 54.9 Ω – 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω
150 130 140 400 250 100 70 170
RT chosen for 50 Ω characteristic input impedance. RO chosen for characteristic output impedance.