a FEATURES 10 ps Delay Resolution 2.5 ns to 10 s Full-Scale Range Fully Differential Inputs Separate Trigger and Reset Inputs Low Power Dissipation—310 mW MIL-STD-883 Compliant Versions Available APPLICATIONS ATE Pulse Deskewing Arbitrary Waveform Generators High Stability Timing Source Multiple Phase Clock Generators
Digitally Programmable Delay Generator AD9500 FUNCTIONAL BLOCK DIAGRAM CEXT
TRIGGER TRIGGER RESET
AD9500 DIFFERENTIAL ANALOG INPUT STAGE
TIMING CONTROL CIRCUIT
ECL VOLTAGE REFERENCE
Q INTERNAL DAC QR
The AD9500 is a digitally programmable delay generator, which provides programmed delays, selected through an 8-bit digital code, in resolutions as small as 10 ps. The AD9500 is constructed in a high performance bipolar process, designed to provide high speed operation for both digital and analog circuits.
21 D 0 (LSB)
TOP VIEW (Not to Scale)
D7 (MSB) 5
25 D (LSB) 0
24 LATCH ENABLE
OFFSET ADJUST 7 NC 8
23 GROUND 22 NC
TOP VIEW (Not to Scale)
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19 ECL COMMON
LATCH OFFSET ENABLE ADJUST
The AD9500 is available as an industrial temperature range device, –25°C to +85°C, and as an extended temperature range device, –55°C to +125°C. Both grades are packaged in a 24-lead cerdip (0.3" package width), as well as 28-leaded and leadless surface mount packages. The AD9500 is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD9500/883B data sheet for detailed specifications.
The digital control data is passed to the AD9500 through a transparent latch controlled by the LATCH ENABLE signal. In the transparent mode, the internal DAC of the AD9500 will attempt to follow changes at the inputs. The LATCH ENABLE is otherwise used to strobe the digital data into the AD9500 latches.
The AD9500 employs differential TRIGGER and RESET inputs which are designed primarily for ECL signal levels but function with analog and TTL input levels. An onboard ECL reference midpoint allows both of the inputs to be driven by either single ended or differential ECL circuits. The AD9500 output is a complementary ECL stage, which also provides a Q R parallel output circuit to facilitate reset timing implementations.
D0 D1 D2 D3 D4 D5 D6 D7 (LSB)
NC = NO CONNECT
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